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| (R) XC4000E Logic Cell Array Family Product Preview Features * Third Generation Field-Programmable Gate Arrays - On-chip ultra-fast RAM with synchronous write option - Dual-port RAM option - Fully PCI compliant - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry-propagation circuit - Wide edge decoders (four per edge) - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution network * Flexible Array Architecture - Programmable logic blocks and I/O blocks - Programmable interconnects and wide decoders * Sub-micron CMOS Process - High-speed logic and Interconnect - Low power consumption * Systems-Oriented Features - IEEE 1149.1-compatible boundary-scan logic support - Programmable output slew rate (2 modes) - Programmable input pull-up or pull-down resistors - 12-mA sink current per output - 24-mA sink current per output pair * Configured by Loading Binary File - Unlimited reprogrammability - Six programming modes * XACT Development System runs on '386/'486/ Pentium-type PC, Apollo, Sun-4, and Hewlett-Packard 700 series - Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD - Fully automatic partitioning, placement and routing - Interactive design editor for design optimization - 288 macros, 34 hard macros, RAM/ROM compiler Description The XC4000E family of Field-Programmable Gate Arrays (FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array. The XC4000E family provides a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). XC4000E devices have generous routing resources to accommodate the most complex interconnect patterns. They are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data can be written into the FPGA (slave and peripheral modes). The XC4000E family is supported by powerful and sophisticated software, covering every aspect of design: from schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation of the configuration bit stream. FPGAs are ideal for shortening the design and development cycle, but they also offer a cost-effective solution for production rates well beyond 1,000 systems per month. The XC4000E family is a superset of the popular XC4000 family. For a detailed description of the device architecture, configuration methods, pin functionality, package pin-outs and dimensions, see the Xilinx Programmable Logic Data Book. The following pages describes the new features of the XC4000E family and list electrical and timing parameters. Table 1. The XC4000E Family of Field-Programmable Gate Arrays Device Appr. Gate Count CLB Matrix Number of CLBs Number of Flip-Flops Max Decode Inputs (per side) Max RAM Bits Number of IOBs XC4003E 3,000 10 x 10 100 360 30 3,200 80 XC4005E 5,000 14 x 14 196 616 42 6,272 112 XC4006E 6,000 16 x 16 256 768 48 8,192 128 XC4008E 8,000 18 x 18 324 936 54 10,368 144 XC4010E 10,000 20 x 20 400 1,120 60 12,800 160 XC4013E 13,000 24 x 24 576 1,536 72 18,432 192 XC4020E XC4025E 20,000 28 x 28 784 2,016 84 25,088 224 25,000 32 x 32 1,024 2,560 96 32,768 256 1 XC4000E Logic Cell Array Family XC4000E compared to XC4000 Any XC4000E device is a 100% compatible superset of the equivalent XC4000 device, not only functionally, but also electrically, and in pin-out and configuration bitstream. The XC4000E devices have the following additional functions, most of which are invoked through options in the configuration bitstream: IOB Clock Enable The two flip-flops in each IOB have a common clock enable input,which through configuration can be activated individually for the input or output flip-flop or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This makes the IOBs more versatile, and avoids the need for clock gating. Synchronous RAM The two RAMs in any CLB can be changed to synchronous write operation. In this synchronous mode, the internal write operation is controlled by the same clock that drives the flip-flops. The clock polarity is programmable for the RAM (both F and G function generators together), but is independent of the chosen flip-flop polarity. Address, Data, and WE inputs are latched by this rising or falling clock edge, and a short internal write pulse is generated right after the clock edge. This self-timed write operation is thus effectively edge-triggered. The read operation is not affected by this change to a synchronous write. Output Drivers The output pull-up structure can be globally configured to be either a TTL-like totem-pole (n-channel pull-up transistor, pulling to a voltage one threshold below Vcc, just like XC4000) or to be CMOS (p-channel pull-up transistor pulling to Vcc). Also, the configurable pull-up resistor in XC4000E is a p-channel transistor that pulls to Vcc, whereas in XC4000 it is an n-channel transistor that pulls to a voltage one threshold below Vcc. Input Thresholds The input thresholds can be globally configured for either TTL ( 1.2 V threshold) or CMOS ( 2.5 V threshold ), just like XC2000 and XC3000 inputs. Note that the two global adjustments of input threshold and output level are independent of each other. Dual-Port RAM A separate option converts the 16 x 2 RAM in any CLB into a 16 x 1 dual-port RAM. In this mode, any operation that writes into the F-RAM, automatically also writes into the GRAM, using the F address. The G-address can, therefore, not be used to write into the G-RAM. The CLB can thus be used as an asymmetrical dual-port RAM, with F being the read address for the F-RAM and the write address for both F- and G-RAM, while G is the read address for the G-RAM. Note that F and G can still be independent read addresses, as they are in XC4000. The two RAMs together have one read/write port using the F address, and one read-only port using the G address. Each CLB can be configured as function generators either asynchronous single-port, synchronous single-port, or synchronous dual-port. Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Mode-Pin Pull-Up Resistors During configuration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be left unconnected. For user mode, the three mode inputs can individually be configured with or without weak pull-up or pull-down resistors The PROGRAM input pin has a permanent weak pull-up. Soft Startup Like XC3000A, the XC4000E family has "Soft Startup". When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual configuration option. H-Function Generator In XC4000E, the H function generator is more versatile. Its inputs can come not only from the F and G function generators but also from up to three control input lines. The H function generator can be totally or partially independent of the other two function generators. 2 IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Input Propagation Delays Pad to I1, I2 Pad to I1, I2, via transparent latch (no delay) Pad to I1, I2, via transparent latch (with delay) Clock (IK) toI1, I2, (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Set-up Time (Note 3) Pad to Clock (IK), no delay Pad to Clock (IK) with delay Hold Time (Note 3) Pad to Clock (IK), no delay Pad to Clock (IK) with delay Output Propagation Delays Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (slew-rate independent) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High or Low time Global Set/Reset Delay from GSR net through Q to I1, I2 Delay from GSR net to Pad GSR width* Symbol Min -4 Max -3 Min Max -2 Min Max Units ADVANCE INFORMATION TPID TPLI TPDLI TIKRI TIKLI TPICK TPICKD TIKPI TIKPID 2.5 3.6 7.1 2.8 3.0 ns ns ns ns ns ns ns ns ns 4.7 8.3 0 0 TOKPOF TOKPOS TOPF TOPS TTSHZ TTSONF TTSONS TOOK TOKO TCH/TCL TRRI TRPO TMRW 4.6 11.2 5.8 12.4 4.2 8.1 14.7 ns ns ns ns ns ns ns ns ns ns ns ns ns 3.7 0 4.0 7.2 18.9 * Timing is based on the XC4005E. For other devices see XACT timing calculator. ** See preceding page Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see pages 8-8 through 8-10. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source. 3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time, subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero. Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK. 3 XC4000E Logic Cell Array Family CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs C inputs via H' to X/Y outputs CLB Fast Carry Logic Operand inputs (F1,F2,G1,G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1,F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators. Sequential Delays Clock K to outputs Q Set-up Time before Clock K F/G inputs F/G inputs via H' C inputs via H1 C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F'/G' CIN input via F'/G' and H' Hold Time after Clock K F/G inputs F/G inputs via H' C inputs via H1 C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Master Set/Reset* Width (High or Low) Delay from Global Set/Reset net to Q Symbol Min -4 Max -3 Min Max -2 Min Max Units TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THHCK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ ADVANCE INFORMATION TILO TIHO THHO 2.0 3.6 2.9 ns ns ns 2.6 4.4 1.7 3.3 0.7 ns ns ns ns ns 2.4 ns 2.3 4.0 3.3 1.9 2.6 1.7 ns ns ns ns ns ns ns ns 0 0 0 0 0 0 ns ns ns ns ns ns 4.0 4.0 ns ns 4.0 4.0 ns ns 18.9 14.4 ns ns * Timing is based on the XC4005E. For other devices see XACT timing calculator. 4 |
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